Company: Synopsys | Location: Bangalore | Exp: 0-2 Years
We’re looking for a R&D engineer in the ProtoCompiler R&D team in Bangalore for the following role.
You would be responsible for designing, developing, troubleshooting, debugging and maintaining large and efficient software systems for partitioning, logic, timing optimization, technology mapping steps of the FPGA prototyping software.
You would be expected to:
Given a requirement or functional specification, design and implement efficient data structures and algorithms in C/C++.
Work with AE team in test planning, execution and customer support.
Maintain and support existing product and features.
B.Tech/M. Tech in CS/EE from a reputed institute.
Sound knowledge in data structures, graph algorithms and C/C++ programming on Windows/Unix.
Familiarity in digital logic design.
Familiarity with Verilog/VHDL RTL level designs, timing constraints, static timing analysis.
0-2 years of experience in designing, developing and maintaining large EDA software.
Working knowledge of FPGA prototyping tools and flows is a plus.
Req Id: 27677BR